A new method for characterization of gate overlap capacitances and effective channel size in MOSFETs. (September 2019)

• Record Type: Journal Article
• Authors: Tomaszewski, Daniel; Głuszko, Grzegorz; Kucharski, Krzysztof; Malesińska, Jolanta
• Is Part Of: Solid-state electronics. Volume 159(2019)
• Page Start: 184
• Page End: 190
• Publication Date: 2019-09
• Subjects: MOSFET -- Test structure -- Parameter extraction -- C-V characteristics -- Overlap capacitances -- Channel shortening -- Channel narrowing; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.03.058
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices.