Cite
HARVARD Citation
Rao, M. et al. (2018). An efficient implementation of FPGA based high speed IPSec (AH/ESP) core. International journal of internet protocol technology. pp. 97-109. [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Rao, M. et al. (2018). An efficient implementation of FPGA based high speed IPSec (AH/ESP) core. International journal of internet protocol technology. pp. 97-109. [Online].