An efficient implementation of FPGA based high speed IPSec (AH/ESP) core. (2018)

• Record Type: Journal Article
• Authors: Rao, Muzaffar; Newe, Thomas; Omerdic, Edin; Dooly, Gerard; Lewis, Elfed; Toal, Daniel
• Is Part Of: International journal of internet protocol technology. Volume 11:Number 2(2018)
• Page Start: 97
• Page End: 109
• Publication Date: 2018
• Subjects: internet protocol security -- IPSec -- field programmable gate array -- FPGA -- authentication header -- AH -- encapsulation security payload -- ESP -- secure hash algorithm-3 -- SHA-3 -- advanced encryption standard -- AES; File Transfer Protocol (Computer network protocol) -- Periodicals; Multicasting (Computer networks) -- Periodicals; 004.678
• Languages: English
• ISSNs: 1743-8209

Abstract

The IPSec is used to secure the IP traffic. The IPSec protocol was designed to fulfil the need to provide security at the network level, so that all the higher-layer protocols in the OSI model could take advantage of it. The implementation of IPSec is a computationally heavy task that affects the high speed network performance. To overcome this issue, the best possible solution is hardware implementation. For a hardware implementation the FPGA platform is considered as one of the best solutions because of its re-configurability and high performance capabilities. The work presented here gives a complete FPGA based implementation of IPSec. This includes both (AH and ESP) IPSec protocol formats. Both IPSec formats are implemented using transport mode and tunnel mode operations. IPSec is not bounded to use any specific cryptographic algorithms; here IPSec is used with the AES and SHA-3 algorithms to provide confidentiality and integrity services respectively.