Modelling and extraction procedure for gate insulator and fringing gate capacitance components of an MIS structure. (20th June 2016)

• Record Type: Journal Article
• Authors: Tinoco, J C; Martinez-Lopez, A G; Lezama, G; Mendoza-Barrera, C; Cerdeira, A; Estrada, M
• Is Part Of: Semiconductor science and technology. Volume 31:Number 7(2016:Jul.)
• Publication Date: 2016-06-20
• Subjects: extrinsic gate capacitance -- capacitance extraction -- fringing capacitance -- EOT; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/0268-1242/31/7/075011
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: CMOS technology has been guided by the continuous reduction of MOS transistors used to fabricate integrated circuits. Additionally, the use of high- k dielectrics as well as a metal gate electrode have promoted the development of nanometric MOS transistors. Under this scenario, the proper modelling of the gate capacitance, with the aim of adequately evaluating the dielectric film thickness, becomes challenging for nanometric metal-insulator-semiconductor (MIS) structures due to the presence of extrinsic fringing capacitance components which affect the total gate capacitance. In this contribution, a complete intrinsic–extrinsic model for gate capacitance under accumulation of an MIS structure, together with an extraction procedure in order to independently determine the different capacitance components, is presented. ATLAS finite element simulation has been used to validate the proposed methodology.