Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes. (9th June 2016)

• Record Type: Journal Article
• Authors: Seoane, N; Aldegunde, M; Nagy, D; Elmessary, M A; Indalecio, G; García-Loureiro, A J; Kalna, K
• Is Part Of: Semiconductor science and technology. Volume 31:Number 7(2016:Jul.)
• Publication Date: 2016-06-09
• Subjects: Monte Carlo -- quantum-corrections -- drift-diffusion -- III-V materials -- Si -- scaling; 8530Tv -- 0705Tp; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/0268-1242/31/7/075005
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: We investigate the performance and scalability of III-V-OI In0.53 Ga0.47 As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths ( L G ) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON / I OFF ratio (5.9 × 10 4 when L G = 12.8 nm and 5.7 × 10 4 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.