ESD characterization of multi-finger RF nMOSFET transistors by TLP and transient interferometric mapping technique. Issue 9 (August 2015)

• Record Type: Journal Article
• Authors: Rigato, Matteo; Fleury, Clément; Heer, Michael; Capriotti, Mattia; Simbürger, Werner; Pogany, Dionyz
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 9/10(2015)
• Page Start: 1471
• Page End: 1475
• Publication Date: 2015-08
• Subjects: Radio frequency nMOSFET -- Electrostatic discharge (ESD) -- Transmission line pulse (TLP) -- Transient interferometric mapping technique (TIM); Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.06.019
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The ESD robustness of multi-finger nMOSFET transistors in an advanced RF CMOS technology has been analysed by both TLP and, for the first time, by transient interferometric mapping (TIM) technique. Failure current It2 has been studied for different source, gate and bulk contact grounding configurations, for TLP pulse duration between 25 ns and 550 ns and TLP rise time of 1 ns and 10 ns. The lateral distribution of dissipated thermal energy during a TLP pulse has been measured by TIM. The ESD failures for selected pad configurations are investigated by DC-IV and physical failure analysis. The highest (lowest) It2 has been revealed for floating (grounded) gate and bulk pads, and attributed to the pn junction (gate oxide) damage. Highlights: ESD characterization of RF nMOSFET in different pad configurations TLP pulse duration and rise time studies of two selected configurations Homogeneous power distribution during TLP pulse in both cases Gate oxide breakdown and thermal failures lead to high It2 variation.