A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. Issue 8 (July 2015)

• Record Type: Journal Article
• Authors: Yadav, Nandakishor; Jain, Shikha; Pattanaik, Manisha; Sharma, G.K.
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 8(2015)
• Page Start: 1131
• Page End: 1143
• Publication Date: 2015-07
• Subjects: FinFET -- SRAM -- Process variation -- Evolutionary algorithm -- Optimization -- Stability; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.05.014
• Languages: English
• ISSNs: 0026-2714

Abstract

Highlights: Process variation aware SRAM design using proposed stability model. SRAM cell optimization technique for maximum yield. Optimization of SRAM cell using evolutionary algorithms. Stability and performance analysis for optimize IDG FinFET based PPN 10T SRAM cell. Abstract: Technology enhancement has increased sensitivity of process variations of scaled SRAM on the verge of instability. This demands a process variation (PV) aware stability model for the modern SRAM. This paper first analyzes PV severity on readability, writability and static leakage current and provides a statistical model. The paper further improves the proposed model by using curve fitting method for stability modeling and modified Least Mean Square with first order differentiation to extract best fitting parameters. The resulting model exhibits characteristics of standard current voltage equation based model. A evolutionary optimization technique is proposed to achieve optimal cell dimension for process tolerant SRAM. The resulting SRAM is tested for worst case stability analysis using Gaussian distribution based statistical approach. Simulation results show that the resulting optimized SRAM improves read, standby and word line write margins by 4%, 4% and 23%, respectively.