Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach. (December 2017)

• Record Type: Journal Article
• Authors: Chakraborty, S; Dasgupta, A; Das, R; Kar, M; Kundu, A; Sarkar, C K
• Is Part Of: Journal of semiconductors. Volume 38:Number 12(2017:Dec.)
• Publication Date: 2017-12
• Subjects: 14 nm -- double gate MOSFET -- look-up table -- VerilogA; 2560; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/38/12/124001
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.