Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs. (June 2015)

• Record Type: Journal Article
• Authors: Koyama, M.; Cassé, M.; Barraud, S.; Ghibaudo, G.; Iwai, H.; Faynot, O.; Reimbold, G.
• Is Part Of: Solid-state electronics. Volume 108(2015)
• Page Start: 36
• Page End: 41
• Publication Date: 2015-06
• Subjects: Si nanowire MOSFETs -- Omega-gate -- Strained-SOI -- Surface orientation -- Low-frequency noise -- Oxide trap density; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2014.12.010
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.