Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide. (September 2017)

• Record Type: Journal Article
• Authors: Tallarico, A.N.; Reggiani, S.; Magnone, P.; Croce, G.; Depetro, R.; Gattari, P.; Sangiorgi, E.; Fiegna, C.
• Is Part Of: Microelectronics and reliability. Volume 76/77(2017)
• Page Start: 475
• Page End: 479
• Publication Date: 2017-09
• Subjects: Hot-carrier degradation -- Interface trap -- ON-state stress -- LDMOS transistor -- Modelling -- Reliability; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.07.043
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device. Highlights: The hot-carrier degradation is fully reproduced in the frame of TCAD simulations. Physics-based models are used providing the degradation kinetics. The single high energetic particle is the dominant process inducing bond-breakage. Charge trapping is spatially localized at the selective Si/SiO2 LOCOS interface.