Cite
APA Citation
Ramos, A., Maestro, J. A., & Reviriego, P. (2017). characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. Microelectronics and reliability, 78, 205–211. http://access.bl.uk/ark:/81055/vdc_100052140362.0x000053