Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor. (April 2017)

• Record Type: Journal Article
• Authors: Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.
• Is Part Of: Superlattices and microstructures. Volume 104(2017)
• Page Start: 470
• Page End: 476
• Publication Date: 2017-04
• Subjects: High-k -- SRAM -- Junctionless transistor -- Dual metal gate engineering -- TCAD; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2017.03.012
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2 ) than Silicon Oxide (SiO2 ). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2 . It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2 . Highlights: Dual Metal Surround Gate Junctionless Transistor (DMSGJLT). Band structure analysis to analyse the subthreshold and leakage parameters of the device with various high-k dielectrics. Estimation of tunnelling path. Capacitance analysis to find the charge holding capability of the high-k dielectric based device. Implementation of 6T SRAM memory circuit using SiO2 and HfO2 based DMSGJLT.