Sub-15 nm gate-all-around field effect transistors on vertical silicon nanowires. (April 2017)

• Record Type: Journal Article
• Authors: Larrieu, G.; Guerfi, Y.; Han, X.L.; Clément, N.
• Is Part Of: Solid-state electronics. Volume 130(2017)
• Page Start: 9
• Page End: 14
• Publication Date: 2017-04
• Subjects: 3D transistors -- Nanowire -- Gate-all-around -- MOS scaling; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2016.12.008
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Vertical silicon nanowire technology with a high degree of process control (short gate length of 14 nm). DC and LFN characterization of such a device. First proof of concept of CMOS inverters based on scaled vertical silicon nanowire architecture. Demonstration of multi-threshold voltage platform based on multiple NW diameter devices. Abstract: A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.