Analytical and finite element methodology modeling of the thermal management of 3D IC with through silicon via. Issue 4 (5th September 2016)

• Record Type: Journal Article
• Authors: Wu, Mei-Ling; Lan, Jia-Shen
• Is Part Of: Soldering & surface mount technology. Volume 28:Issue 4(2016)
• Page Start: 177
• Page End: 187
• Publication Date: 2016-09-05
• Subjects: Modelling -- Finite element modelling (FEM) -- Interconnections -- Thermal fatigue -- Fatigue -- Joint resistance -- Thermal management -- 3D IC package -- Coefficient thermal expansion -- Through-silicon-vias -- Finite element methodology -- Thermal failure; Brazing -- Periodicals; Solder and soldering -- Periodicals; 671.5605
• DOI: 10.1108/SSMT-04-2016-0008
• Languages: English
• ISSNs: 0954-0911

Abstract

Abstract : Purpose: This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs). Design/methodology/approach: This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace's equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package. Findings: This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package. Research limitations/implications: Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed. Practical implications: The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board. Social implications: In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model. Originality/value: The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.