A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS. (November 2016)

• Record Type: Journal Article
• Authors: Shen, Yi; Liu, Shubin; Zhu, Zhangming
• Is Part Of: Microelectronics journal. Volume 57(2016)
• Page Start: 26
• Page End: 33
• Publication Date: 2016-11
• Subjects: Pipelined SAR ADC -- Zero-crossing -- Dual-phase charge transfer -- Low Power; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.09.002
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A two-stage pipelined SAR (Successive Approximation Register) ADC is presented. The ADC consists of a 6-bit SAR-based MDAC and a 7-bit SAR ADC with 1-bit redundancy to relax the requirement for accuracy. The zero-crossing-based circuit is introduced as a replacement for the conventional OTA. The dual-phase charge transfer technique is used to ensure high bandwidth and high accuracy of the MDAC. The prototype was fabricated in a 0.18 µm standard CMOS technology. At a supply voltage of 1.8 V and a sample rate of 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 66.53 dB and consumes 5.5 mW, resulting in a figure of merit (FOM) of 63.5 fJ/conversion-step. The ADC occupies an active area of 0.44 mm 2 .