Cite
HARVARD Citation
Shen, Y. et al. (2016). A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS. Microelectronics journal. pp. 26-33. [Online].
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Shen, Y. et al. (2016). A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS. Microelectronics journal. pp. 26-33. [Online].