A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS. (November 2016) - Shen, Yi; Liu, Shubin; Zhu, Zhangming
Abstract: A two-stage pipelined SAR (Successive Approximation Register) ADC is presented. The ADC consists of a 6-bit SAR-based MDAC and a 7-bit SAR ADC with 1-bit redundancy to relax the requirement for accuracy. The zero-crossing-based circuit is introduced as a replacement for the conventional OTA. The dual-phase charge transfer technique is used to ensure high bandwidth and high accuracy of the MDAC. The prototype was fabricated in a 0.18 µm standard CMOS technology. At a supply voltage of 1.8 V and a sample rate of 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 66.53 dB and consumes 5.5 mW, resulting in a figure of merit (FOM) of 63.5 fJ/conversion-step. The ADC occupies an active area of 0.44 mm 2 .