Prediction of deformation during manufacturing processes of silicon interposer package with TSVs. (October 2016)

• Record Type: Journal Article
• Authors: Kim, Yeonsung; Park, Ah-Young; Kao, Chin-Li; Su, Michael; Black, Bryan; Park, Seungbae
• Is Part Of: Microelectronics and reliability. Volume 65(2016)
• Page Start: 234
• Page End: 242
• Publication Date: 2016-10
• Subjects: Package stress -- Simulation -- Through silicon via (TSV) interposer -- Warpage -- 2.5D package; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2016.07.153
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature ( T g ) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface. Highlights: A thermal deformation of a through silicon via (TSV) interposer package during the manufacturing process was measured. 3D FEA model was developed based on the experimental result and an optimization study was performed A low CTE and a thick substrate is the most efficient way to minimize the package warpage. To minimize the stress between the interposer and underfill, low modulus, low CTE, and high Tg underfill is recommended.