Cite
APA Citation
Shaji, N., & Bonifus, P. (2016). design of AES Architecture With Area and Speed Tradeoff. Procedia technology, 24, 1135–1140. http://access.bl.uk/ark:/81055/vdc_100034090837.0x000018
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Shaji, N., & Bonifus, P. (2016). design of AES Architecture With Area and Speed Tradeoff. Procedia technology, 24, 1135–1140. http://access.bl.uk/ark:/81055/vdc_100034090837.0x000018