Design of AES Architecture With Area and Speed Tradeoff. (2016)

• Record Type: Journal Article
• Authors: Shaji, Neenu; Bonifus, P.L.
• Is Part Of: Procedia technology. Volume 24(2016)
• Page Start: 1135
• Page End: 1140
• Publication Date: 2016
• Subjects: Security -- Cryptography -- AES -- Encryption -- Decryption -- Field Programmable Gate Array(FPGA) -- RTL; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.05.066
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: AES, is the well-accepted cryptographic algorithm which could be utilized to ensure security of electronic information since it is proven to be resistive to most of the attacks. In this work, we present the AES-128 encryption and decryption circuit using area optimized iterative architecture. Here the technique used to obtain a lower area delay product is to map the transformations to 8 bit hardware while keeping the datapath to be 128 bit. A control unit is designed to keep track of the transformations. The proposed architecture have been implemented on the most recent Xilinx Spartan FPGA, their area and delay are compared with the previous works and it is proved that proposed technique has lower area coverage and delay.