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APA Citation
Kaur, B., Sharma, A., Alam, N., Manhas, S., & Anand, B. (2016). a variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectronics journal, 53, 45–55. http://access.bl.uk/ark:/81055/vdc_100032676620.0x000056