Cite
HARVARD Citation
Kaur, B. et al. (2016). A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectronics journal. pp. 45-55. [Online].
This is an interim version of our Electronic Legal Deposit Catalogue-eJournals and eBooks while we continue to recover from a cyber-attack.
Kaur, B. et al. (2016). A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectronics journal. pp. 45-55. [Online].