Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process. (February 2016)

• Record Type: Journal Article
• Authors: Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan
• Is Part Of: Solid-state electronics. Volume 116(2016)
• Page Start: 80
• Page End: 87
• Publication Date: 2016-02
• Subjects: Electrostatic discharge (ESD) -- Drain-extended NMOS (DeNMOS) -- Robustness; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.11.033
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: The ESD performance of DeNMOS are divided into three distinguishing phases. Actual instances of failure analysis for damages of GG-DeNMOS are given. Many modified methods to achieve high ESD performance of DeNMOS are listed. Abstract: Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.