Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs*Project supported by the National 02 IC Projects and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences. (April 2015)

• Record Type: Journal Article
• Authors: Xu, Miao; Yin, Huaxiang; Zhu, Huilong; Ma, Xiaolong; Xu, Weijia; Zhang, Yongkui; Zhao, Zhiguo; Luo, Jun; Yang, Hong; Li, Chunlong; Meng, Lingkuan; Hong, Peizhen; Xiang, Jinjuan; Gao, Jianfeng; Xu, Qiang; Xiong, Wenjuan; Wang, Dahai; Li, Junfeng; Zhao, Chao; Chen, Dapeng; Yang, Simon; Ye, Tianchun
• Is Part Of: Journal of semiconductors. Volume 36:Number 4(2015:Apr.)
• Page Start: 263
• Publication Date: 2015-04
• Subjects: Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/36/4/044007
• Languages: English
• ISSNs: 1674-4926

Abstract

<abstract> <title>Abstract</title> <p>Sub-20 nm node bulk FinFET PMOS devices with an all-last high-<italic>k</italic>/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device's scaling.</p> </abstract>