441. Deploying massive runs of evolutionary algorithms with ECJ and Hadoop: Reducing interest points required for face recognition. (September 2018) Authors: Chávez, Francisco; Fernández de Vega, Francisco; Lanza, Daniel; Benavides, César; Villegas, Juan; Trujillo, Leonardo; Olague, Gustavo; Román, Graciela Other Names: Bland Wesley guest-editor.; Erez Mattan guest-editor.; Hidalgo J Ignacio guest-editor.; Fernández de Vega Francisco guest-editor.; Mercier Guillaume guest-editor. Journal: International journal of high performance computing applications Issue: Volume 32:Number 5(2018) Page Start: 706 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
442. Design and implementation of a cloud computing platform for electromagnetic modelling. (2015) Authors: Caragnano, Giuseppe; Mossucca, Lorenzo; Francavilla, Matteo Alessandro; Ruiu, Pietro; Terzo, Olivier Journal: International journal of high performance computing and networking Issue: Volume 8:Number 3(2015) Page Start: 248 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
443. Design and implementation of an Openflow SDN controller in NS-3 discrete-event network simulator. (8th May 2019) Authors: Poncea, Ovidiu Mihai; Pistirica, Andrei Sorin; Moldoveanu, Florica; Asavei, Victor Journal: International journal of high performance computing and networking Issue: Volume 14:Number 1(2019) Page Start: 17 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
444. Design and verification of an ARM Watchdog Timer using UVM. (12th December 2022) Authors: Ragamathana, R.; Prathiba, A.; Basha, Shaik Chand Journal: International journal of high performance systems architecture Issue: Volume 11:Number 2(2022) Page Start: 85 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
445. Design and VLSI implementation of power efficient processor for object localisation in large WSN. (1st January 2013) Authors: Bag, Joyashree; Sahoo, Rashmi Ranjan; Dutta, Pranab Kishore; Sarkar, Subir Kumar Journal: International journal of high performance systems architecture Issue: Volume 4:Number 4(2013) Page Start: 204 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
446. Design of a router for network-on-chip. (15th October 2007) Authors: Bahn, Jun Ho; Lee, Seung Eun; Bagherzadeh, Nader Journal: International journal of high performance systems architecture Issue: Volume 1:Number 2(2007) Page Start: 98 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
447. Design of optimum fault tolerant decoder using five input majority voter based on quantum dot cellular automata. (25th March 2022) Authors: Husain, Shiraz; Gupta, Namit Journal: International journal of high performance systems architecture Issue: Volume 11:Number 1(2022) Page Start: 47 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
448. Design of the notification system for failure detectors. (8th June 2009) Authors: Hayashibara, Naohiro; Takizawa, Makoto Journal: International journal of high performance computing and networking Issue: Volume 6:Number 1(2009) Page Start: 25 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
449. Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4 ≤ m ≤ 10) compressors. (1st January 2013) Authors: Mehrabi, Shima; Mirzaee, Reza Faghih; Zamanzadeh, Sharareh; Navi, Keivan; Hashemipour, Omid Journal: International journal of high performance systems architecture Issue: Volume 4:Number 4(2013) Page Start: 231 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
450. Designing a graphics processing unit accelerated petaflop capable lattice Boltzmann solver: Read aligned data layouts and asynchronous communication. (May 2017) Authors: Robertsén, Fredrik; Westerholm, Jan; Mattila, Keijo Other Names: Aldinucci Marco guest-editor.; Brorsson Mats guest-editor.; D'Agostino Daniele guest-editor.; Daneshtalab Masoud guest-editor.; Kilpatrick Peter guest-editor.; Leppänen Ville guest-editor. Journal: International journal of high performance computing applications Issue: Volume 31:Number 3(2017) Page Start: 246 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗