Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4 ≤ m ≤ 10) compressors. (1st January 2013)

• Record Type: Journal Article
• Authors: Mehrabi, Shima; Mirzaee, Reza Faghih; Zamanzadeh, Sharareh; Navi, Keivan; Hashemipour, Omid
• Is Part Of: International journal of high performance systems architecture. Volume 4:Number 4(2013)
• Page Start: 231
• Page End: 241
• Publication Date: 2013-01-01
• Subjects: multiplier -- m:3 compressor -- wide counter -- partial product reduction -- multiplexer -- exclusive-OR -- XOR; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Compressors play an important role for partial products reduction in the multiplication process. This paper presents a new implementation for the second phase of a 16 × 16-bit multiplier block using wide m:3 compressors such as 8:3, 9:3, and 10:3. Transistor-level and gate-level analysis are conducted to simulate, test, and implement the proposed structures in 90 nm CMOS technology. The proposed structure has 16% higher efficiency compared when only up to 7:3 counters are employed.