Design of a router for network-on-chip. (15th October 2007)

• Record Type: Journal Article
• Authors: Bahn, Jun Ho; Lee, Seung Eun; Bagherzadeh, Nader
• Is Part Of: International journal of high performance systems architecture. Volume 1:Number 2(2007)
• Page Start: 98
• Page End: 105
• Publication Date: 2007-10-15
• Subjects: network-on-chip -- NoC architecture -- on-chip interconnection -- adaptive routing -- mesh network -- router design -- VLSI; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput and simple routing algorithm even if basic network problems such as deadlock and livelock are considered. We develop a new packet definition to support different requirements in an MIMD message passing architecture and also verify its efficiency by comparing simulation results with various routing algorithms. Major contributions of this paper are the design of Network-on-Chip (NoC) architecture adopting a minimal adaptive routing algorithm with competitive performance and feasible design complexity, thus satisfying all the stated design goals. The proposed adaptive routing algorithm and NoC architecture offer nearly optimal performance. This can be shown by comparing with the near-optimal worst-case throughput routing algorithm for 2D-mesh networks. By providing a uniform way of constructing such network architecture, its scalability can be easily accomplished. Moreover, this network architecture can be applied to different SoC developments.