1. 65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography. Issue 2 (15th December 2017) Authors: Asif, Shahzad; Andersson, Oskar; Rodrigues, Joachim; Kong, Yinan Journal: IET computers & digital techniques Issue: Volume 12:Issue 2(2018) Page Start: 62 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA. Issue 4 (22nd May 2017) Authors: Zhang, Hao; Chen, Dongdong; Ko, Seok‐Bum Journal: IET computers & digital techniques Issue: Volume 11:Issue 4(2017) Page Start: 149 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Comparative analysis of network‐on‐chip simulation tools. Issue 1 (5th December 2017) Authors: Khan, Sarzamin; Anjum, Sheraz; Gulzari, Usman Ali; Torres, Frank Sill Journal: IET computers & digital techniques Issue: Volume 12:Issue 1(2018) Page Start: 30 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Dependability analysis of cyber physical systems. Issue 6 (24th October 2017) Authors: Alemayehu, Temesgen Seyoum; Kim, Jai‐Hoon Journal: IET computers & digital techniques Issue: Volume 11:Issue 6(2017) Page Start: 231 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Efficient and scalable cross‐by‐pass‐mesh topology for networks‐on‐chip. Issue 4 (22nd May 2017) Authors: Gulzari, Usman Ali; Anjum, Sheraz; Aghaa, Shahrukh; Khan, Sarzamin; Sill Torres, Frank Journal: IET computers & digital techniques Issue: Volume 11:Issue 4(2017) Page Start: 140 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Evaluation of simulator tools and power‐aware scheduling model for wireless sensor networks. Issue 5 (9th August 2017) Authors: Chéour, Rym; Jmal, Mohamed Wassim; Kanoun, Olfa; Abid, Mohamed Journal: IET computers & digital techniques Issue: Volume 11:Issue 5(2017) Page Start: 173 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Extending multi‐level STT‐MRAM cell lifetime by minimising two‐step and hard state transitions in hot bits. Issue 6 (16th October 2017) Authors: Ahmad, Imtiaz; Imdoukh, Mahmoud; Alfailakawi, Mohammad Gh. Journal: IET computers & digital techniques Issue: Volume 11:Issue 6(2017) Page Start: 214 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Fast and accurate circuit delay model for FPGA architectural exploration. Issue 3 (13th February 2017) Authors: Liu, Qiang; Qian, HanJing Journal: IET computers & digital techniques Issue: Volume 11:Issue 3(2017) Page Start: 117 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
9. Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits. Issue 4 (25th May 2017) Authors: El‐Maleh, Aiman H. Journal: IET computers & digital techniques Issue: Volume 11:Issue 4(2017) Page Start: 159 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
10. Formal verification methodology for real‐time Field Programmable Gate Array. Issue 5 (9th August 2017) Authors: Jabeen, Shaista; Srinivasan, Sudarshan; Shuja, Sana Journal: IET computers & digital techniques Issue: Volume 11:Issue 5(2017) Page Start: 197 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗