Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA. Issue 4 (22nd May 2017)

• Record Type: Journal Article
• Authors: Zhang, Hao; Chen, Dongdong; Ko, Seok‐Bum
• Is Part Of: IET computers & digital techniques. Volume 11:Issue 4(2017)
• Page Start: 149
• Page End: 158
• Publication Date: 2017-05-22
• Subjects: field programmable gate arrays -- floating point arithmetic -- iterative methods; floating‐point multiplication -- field programmable gate array -- DSP blocks -- power‐efficient iterative FP multiplier architecture -- single‐precision operations -- double‐precision operations -- Karatsuba algorithm -- pipeline registers -- Virtex‐5 devices -- Altera Arria‐10 devices -- Xilinx Virtex‐7 -- ASIC platform; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2016.0100
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In this study, an area and power‐efficient iterative floating‐point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single‐precision (SP) and double‐precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look‐up tables (LUTs), and 31.2% less flip‐flops while having 4% faster clock frequency on Virtex‐5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower‐power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex‐7 and Altera Arria‐10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM‐90 nm ASIC platform are reported.