65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography. Issue 2 (15th December 2017)

• Record Type: Journal Article
• Authors: Asif, Shahzad; Andersson, Oskar; Rodrigues, Joachim; Kong, Yinan
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 2(2018)
• Page Start: 62
• Page End: 67
• Publication Date: 2017-12-15
• Subjects: public key cryptography -- residue number systems -- multiplying circuits -- CMOS logic circuits; 65‐nm CMOS low‐energy RNS modular multiplier -- elliptic‐curve cryptography algorithm -- modular multiplication -- Rivest‐Shamir‐Adleman cryptography algorithm -- elliptic curve point multiplication -- modular exponentiation -- Chinese remainder theorem -- residue number system -- 40‐channel RNS moduli‐set -- short‐channel width -- ASIC -- energy dissipation -- low‐voltage ECC -- energy‐efficient ECC; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0017
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic‐curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40‐channel RNS moduli‐set is proposed for this architecture to benefit from the short‐channel width of the RNS moduli‐set. The throughput of the architecture is enhanced by pipelining and pre‐computations. The proposed architecture is fabricated as an ASIC using 65‐nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low‐voltage and energy‐efficient ECCs.