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3. A Modified Scheme to Reduce the Specific Contact Resistivity of NiSi/Si Contacts by Means of Dopant Segregation Technique. (1st January 2017)

4. A Modified Scheme to Reduce the Specific Contact Resistivity of NiSi/Si Contacts by Means of Dopant Segregation Technique. (22nd December 2017)

5. Accurate lifetime prediction for channel hot carrier stress on sub-1 nm equivalent oxide thickness HK/MG nMOSFET with thin titanium nitride capping layer. (July 2016)

6. Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process. (1st January 2015)

8. Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation. (1st January 2019)

9. Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation. (31st May 2019)

10. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs*Project supported by the National 02 IC Projects and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences. (April 2015)