1. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits. (February 2017) Authors: Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L. Journal: Solid-state electronics Issue: Volume 128(2017) Page Start: 37 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Digital and analog TFET circuits: Design and benchmark. (August 2018) Authors: Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L. Journal: Solid-state electronics Issue: Volume 146(2018) Page Start: 50 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages. (January 2016) Authors: Luong, G.V.; Strangio, S.; Tiedemannn, A.; Lenk, S.; Trellenkamp, S.; Bourdelle, K.K.; Zhao, Q.T.; Mantl, S. Journal: Solid-state electronics Issue: Volume 115 Part B(2016) Page Start: 152 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗