Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages. (January 2016)

• Record Type: Journal Article
• Authors: Luong, G.V.; Strangio, S.; Tiedemannn, A.; Lenk, S.; Trellenkamp, S.; Bourdelle, K.K.; Zhao, Q.T.; Mantl, S.
• Is Part Of: Solid-state electronics. Volume 115 Part B(2016)
• Page Start: 152
• Page End: 159
• Publication Date: 2016-01
• Subjects: Si nanowire TFET -- Analog performance -- Gate-all-around -- Inverter -- C-TFET -- Subthreshold slope; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.08.020
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: In this work, strained Si (sSi) nanowire array of n-TFETs with gates all around (GAA) yielding ON-currents of 5 μA/μm at a supply voltage V dd = 0.5 V are presented. Tilted ion implantation with BF2 + into NiSi2 dopant has been used to form a highly doped pocket for the source to channel tunneling junction. These devices indicate sub-threshold slopes (SS) below 60 mV/dec for I d < 10 −4 μA/μm at V ds = 0.1 V at room temperature. Common analog device characteristics have been determined at V dd = 0.5 V resulting in a transconductance g m = 24 μS/μm, transconductance efficiency g m / I d = 23 V −1 and the conductance g d = 0.8 μS/μm normalized to the gate width. Based on the good saturation behavior in the output characteristic, an intrinsic gain of 188 is observed. In addition, we present operation of the first experimental sSi GAA NW C-TFET inverter. In spite of ambipolar behavior, the voltage transfer curves (VTC) indicate wide and constant noise margin levels with steep transitions offering a voltage gain of 25 at V dd = 1 V.