1. Two-stage low power test data compression for digital VLSI circuits. (October 2018) Authors: Thilagavathi, K.; Sivanantham, S. Journal: Computers & electrical engineering Issue: Volume 71(2018) Page Start: 309 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Reconfigurable half-precision floating-point real/complex fused multiply and add unit. (7th July 2020) Authors: Nesam, J. Jean Jenifer; Sivanantham, S. Journal: International journal of material & product technology Issue: Volume 60:Number 1(2020) Page Start: 58 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System. (15th October 2014) Authors: Agarwal, Avni; Harsha, P.; Vasishta, Swati; Sivanantham, S. Other Names: Gao Lixin Academic Editor. Journal: Journal of computer networks and communications Issue: Volume 2014(2014) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Analysis of hardware implementations of deblocking filter for video codecs. (25th September 2020) Authors: Rajabai, C. Prayline; Sivanantham, S. Journal: International journal of material & product technology Issue: Volume 60:Number 2/4(2020) Page Start: 214 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗