Reconfigurable half-precision floating-point real/complex fused multiply and add unit. (7th July 2020)

• Record Type: Journal Article
• Authors: Nesam, J. Jean Jenifer; Sivanantham, S.
• Is Part Of: International journal of material & product technology. Volume 60:Number 1(2020)
• Page Start: 58
• Page End: 72
• Publication Date: 2020-07-07
• Subjects: FMA architecture -- floating-point arithmetic -- half-precision -- FFT processor -- reconfigurable system; Manufacturing processes -- Periodicals; Materials -- Testing -- Periodicals; 620.11
• Languages: English
• ISSNs: 0268-1900

Abstract

Multiplication followed by an addition/subtraction is the common operation in many digital signal and image processing applications. This paper presents a reconfigurable floating-point real/complex fused multiply and add (R/C-FMA) unit using small precision (IEEE-754-2008 16-bit half-precision) format. The developed FMA can be reconfigurable from real to complex based on the control bits. This architecture performs real FMA [( a × b ) + c ], complex FMA {[( a + ib ) × ( c + id )] + ( e + if )} or mixed real and complex FMA {[( a + ib ) × ( c + id )] + e }. The field programmable gate array (FPGA) implementation of R/C-FMA design, utilises the modern features of inbuilt DSP blocks for mantissa multiplication and addition/subtraction. The efficient DSP usage for fp16 FMA design shows a 60% reduction in LUT area when compared to conventional fp32 FMA.