Analysis of hardware implementations of deblocking filter for video codecs. (25th September 2020)

• Record Type: Journal Article
• Authors: Rajabai, C. Prayline; Sivanantham, S.
• Is Part Of: International journal of material & product technology. Volume 60:Number 2/4(2020)
• Page Start: 214
• Page End: 235
• Publication Date: 2020-09-25
• Subjects: VLSI architecture -- deblocking filter -- H264/AVC -- H265/MPEG -- video coding; Manufacturing processes -- Periodicals; Materials -- Testing -- Periodicals; 620.11
• Languages: English
• ISSNs: 0268-1900

Abstract

H.264 and H.265 are the most popular video coding standards used for various applications. These coding standards use multiple modules to perform video compression. Among the various modules, the deblocking filter (DBF) is one of the critical modules in the video codec, which requires extensive computation. It is computationally complicated and critically time-consuming. DBF removes the blocking artefacts caused due to inverse transform, intra-prediction, inter-frame prediction and motion compensated prediction. For the past two decades, the deblocking filtering algorithm is implemented in hardware and research is still going on for realising optimised hardware solutions for this critical module. Efficient hardware implementation of the DBF is essential for high-resolution video applications such as HDTV to increase the decoding throughput, to achieve high speed and to reduce the off-chip memory access cycles. This paper presents an intricate analysis of various hardware architectures of DBF used for H.264 and H.265 coding standards.