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You searched for: Author/Creator Samanta, TuhinaLimit your search
- Samanta, Tuhina [remove] 2
- 621.39 2
- Computer architecture -- Periodicals 2
- Computer engineering -- Periodicals 2
- Computer organization -- Periodicals 2
- Computers -- Periodicals 2
- Digital electronics -- Periodicals 2
- clocks -- integrated circuit design -- trees (mathematics) -- VLSI -- buffer circuits -- three‐dimensional integrated circuits 1
- incorrect noise estimation -- crosstalk noise model -- coupled RLC on‐chip interconnects -- 2D IC -- rectilinear routing algorithm -- crosstalk minimisation -- coupling capacitance -- reduced coupling distance -- fringing capacitance -- unintentional noise -- accurate noise assessment -- 3D IC -- coupling inductance -- 2D integrated circuit interconnects -- 3D integrated circuit interconnects -- deep sub‐micron technology -- circuit design -- overestimation resources -- time‐efficient method -- SPICE -- through‐silicon‐via -- high‐frequency operation -- TSV structure -- substrate resistivity -- guarding TSV termination 1
- integrated circuit noise -- RLC circuits -- three‐dimensional integrated circuits -- integrated circuit modelling -- crosstalk -- SPICE -- integrated circuit interconnections -- integrated circuit design -- network routing 1
- obstacle‐avoiding clock routing tree construction -- multiple TSVs -- effective clock tree design -- chip performance -- clock network -- clock skew -- 3D IC clock tree design algorithm -- dynamic power consumption -- Elmore delay method -- through‐silicon‐vias -- obstacle avoiding abstract clock tree 1