Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC. Issue 6 (18th September 2020)

• Record Type: Journal Article
• Authors: Mondal, Khokan; Das, Subhajit; Samanta, Tuhina
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 6(2020)
• Page Start: 263
• Page End: 271
• Publication Date: 2020-09-18
• Subjects: integrated circuit noise -- RLC circuits -- three‐dimensional integrated circuits -- integrated circuit modelling -- crosstalk -- SPICE -- integrated circuit interconnections -- integrated circuit design -- network routing; incorrect noise estimation -- crosstalk noise model -- coupled RLC on‐chip interconnects -- 2D IC -- rectilinear routing algorithm -- crosstalk minimisation -- coupling capacitance -- reduced coupling distance -- fringing capacitance -- unintentional noise -- accurate noise assessment -- 3D IC -- coupling inductance -- 2D integrated circuit interconnects -- 3D integrated circuit interconnects -- deep sub‐micron technology -- circuit design -- overestimation resources -- time‐efficient method -- SPICE -- through‐silicon‐via -- high‐frequency operation -- TSV structure -- substrate resistivity -- guarding TSV termination; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2020.0010
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub‐micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on‐chip interconnects has been demonstrated. Subsequently, a novel time‐efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through‐silicon‐via (TSV), which is used to connect different dies vertically in a 3D IC. Under high‐frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.