1. Charge-based compact analytical model for triple-gate junctionless nanowire transistors. (August 2016) Authors: Ávila-Herrera, F.; Paz, B.C.; Cerdeira, A.; Estrada, M.; Pavanello, M.A. Journal: Solid-state electronics Issue: Volume 122(2016) Page Start: 23 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Charge-based compact analytical model for triple-gate junctionless nanowire transistors. (August 2016) Authors: Ávila-Herrera, F.; Paz, B.C.; Cerdeira, A.; Estrada, M.; Pavanello, M.A. Journal: Solid-state electronics Issue: Volume 122(2016) Page Start: 23 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
3. Compact model for short-channel symmetric double-gate junctionless transistors. (September 2015) Authors: Ávila-Herrera, F.; Cerdeira, A.; Paz, B.C.; Estrada, M.; Íñiguez, B.; Pavanello, M.A. Journal: Solid-state electronics Issue: Volume 111(2015) Page Start: 196 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
4. Compact model for short-channel symmetric double-gate junctionless transistors. (September 2015) Authors: Ávila-Herrera, F.; Cerdeira, A.; Paz, B.C.; Estrada, M.; Íñiguez, B.; Pavanello, M.A. Journal: Solid-state electronics Issue: Volume 111(2015) Page Start: 196 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
5. Drain current model for short-channel triple gate junctionless nanowire transistors. (August 2016) Authors: Paz, B.C.; Cassé, M.; Barraud, S.; Reimbold, G.; Faynot, O.; Ávila-Herrera, F.; Cerdeira, A.; Pavanello, M.A. Journal: Microelectronics and reliability Issue: Volume 63(2016) Page Start: 1 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
6. Drain current model for short-channel triple gate junctionless nanowire transistors. (August 2016) Authors: Paz, B.C.; Cassé, M.; Barraud, S.; Reimbold, G.; Faynot, O.; Ávila-Herrera, F.; Cerdeira, A.; Pavanello, M.A. Journal: Microelectronics and reliability Issue: Volume 63(2016) Page Start: 1 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
7. Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. (December 2017) Authors: Paz, B.C.; Doria, R.T.; Cassé, M.; Barraud, S.; Reimbold, G.; Vinet, M.; Faynot, O.; Pavanello, M.A. Journal: Microelectronics and reliability Issue: Volume 79(2017) Page Start: 111 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
8. Underestimation of measured self‐heating in nanowires by using gate resistance technique. Issue 23 (1st November 2016) Authors: Mariniello, G.; Cassé, M.; Reimbold, G.; Pavanello, M.A. Journal: Electronics letters Issue: Volume 52:Issue 23(2016) Page Start: 1935 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗