Charge-based compact analytical model for triple-gate junctionless nanowire transistors. (August 2016)

• Record Type: Journal Article
• Authors: Ávila-Herrera, F.; Paz, B.C.; Cerdeira, A.; Estrada, M.; Pavanello, M.A.
• Is Part Of: Solid-state electronics. Volume 122(2016)
• Page Start: 23
• Page End: 31
• Publication Date: 2016-08
• Subjects: 3-D compact model -- Triple-gate JLT -- Nanowire JLT -- SCE -- Fin height capacitance -- Threshold voltage; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2016.04.013
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: A compact analytical model for triple gate junctionless transistors is developed. Junctionless devices from double gate down to nanowires transistors are modeled. An analytical expression for threshold voltage is presented. Short channel effects, mobility degradation and series resistance are covered. The model validation is performed with simulated and experimental results. Abstract: A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 × 10 18 and 1 × 10 19 cm −3 . The developed model is suitable for describing the current–voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters.