Compact model for short-channel symmetric double-gate junctionless transistors. (September 2015)

• Record Type: Journal Article
• Authors: Ávila-Herrera, F.; Cerdeira, A.; Paz, B.C.; Estrada, M.; Íñiguez, B.; Pavanello, M.A.
• Is Part Of: Solid-state electronics. Volume 111(2015)
• Page Start: 196
• Page End: 203
• Publication Date: 2015-09
• Subjects: Compact analytical model -- Double-gate JLT -- SCE model -- JLT; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.06.009
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: An analytical short channel model is developed for junctionless transistors. Subthreshold behavior, velocity saturation, channel shrinking are modeled. Mobility degradation and series resistance were included. Validation for 5 × 10 18 and 1 × 10 19 cm −3 with layer thicknesses of 10 and 15 nm. The model describes accurately the behavior of the transistor. Abstract: In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 10 18 and 1 × 10 19 cm −3, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.