Search

Search Constraints

You searched for: Author/Creator De Rose Cesar A. F. guestEditor.

Search Results

1. A comprehensive performance evaluation of the BinLPT workload‐aware loop scheduler. (19th February 2019)

2. A hybrid CPU‐GPU‐MIC algorithm for minimal hitting set enumeration. (28th November 2018)

3. ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing. (3rd December 2018)

4. DF‐DTM: Dynamic Task Memoization and reuse in dataflow. (3rd September 2018)

5. DTM@GPU: Characterizing and evaluating trace redundancy in GPU. (28th February 2018)

6. Energy efficiency and I/O performance of low‐power architectures. (30th August 2018)

7. Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs. (14th September 2018)

8. Foreword to the special issue of the workshop on high performance computing systems (XVIII Simpósio em Sistemas Computacionais de Alto Desempenho, WSCAD 2017). (7th May 2019)

10. Maximizing the GPU resource usage by reordering concurrent kernels submission. (17th January 2018)