Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs. (14th September 2018)

• Record Type: Journal Article
• Authors: Carrijo Nasciutti, Thiago; Panetta, Jairo; Pais Lopes, Pedro
• Other Names: Boeres Cristina guestEditor.; Bentes Cristiana guestEditor.; Moreno Edward guestEditor.; De Rose Cesar A. F. guestEditor.; Castrol Márcio guestEditor.
• Is Part Of: Concurrency and computation. Volume 31:Number 18(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-09-14
• Subjects: GPGPU -- memory hierarchy -- stencil computation; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.4929
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: This work compares the performance of optimizations that transform replicated global memory accesses into local memory accesses on 3D stencil computations in the NVIDIA Tesla K80 GPGPU. The optimizations reduce global memory contention caused by the set of multiprocessors. Evaluated optimizations are grid tiling, inserting spatial and temporal loops into kernels, register reuse, and some of their combinations. A standardized experiment evaluates performance variation with grid size and stencil size for each optimization. Experimental data show that codes that use these optimizations are up to 3.3 times faster than the classical stencil formulation. It also shows that the most profitable optimization varies with grid and stencil sizes.