A triple-node-upset self-recoverable design based on Schmitt-triggers and C-elements. (May 2023)

• Record Type: Journal Article
• Authors: Xu, Hui; Liu, Chaoming; Ma, Ruijun; Liang, Huaguo; Huang, Zhengfeng; Zhou, Jing; Zhu, Shuo
• Is Part Of: Microelectronics and reliability. Volume 144(2023)
• Publication Date: 2023-05
• Subjects: Triple-node-upset -- Soft error -- Hardened latch -- Circuit reliability; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2023.114977
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: As the semiconductor process development, it is shrinking rapidly for the distance of adjacent transistors in integrated circuits (ICs). Hence, latches are increasingly vulnerable to multiple-node-upset (MNU). To effectively mitigate MNU while keeping lower power consumption and delay, this paper proposed a latch design (namely CS-TNURL). The latch consists of four C-elements (CEs), four Schmitt-triggers (STs), seven transmission gates (TGs), and is capable of triple-node-upset (TNU) self-recovery. Besides, this latch uses fewer transistors and clock gating technique, which results in lower power consumption and D-Q delay. Compared with existing latches with TNU self-recoverability, the simulation has shown the proposed latch reduces power consumption by 70 %, delay by 10.62 %, area overhead by 29.71 %, and the power-delay-product (PDP) by 70.34 % on average, respectively. Additionally, the estimation of process, voltage, and temperature (PVT) variation indicated CS-TNURL has a moderate sensitivity towards the PVT variation. Highlights: The new latch consists of four C-elements and four Schmitt-trigger. There is a low overhead compared to existing same-type structures. Self-recovery from triple-node-upset caused by soft error. Insensitivity to variations in voltage, temperature, and process corner