Dynamic electrostatic-discharge path investigation relied on different impact energies in metal–oxide–semiconductor circuits. (1st April 2023)

• Record Type: Journal Article
• Authors: Xie 谢, Tian-Tian 田田; Wang 王, Jun 俊; Du 杜, Fei-Bo 飞波; Yu 郁, Yang 扬; Cai 蔡, Yan-Fei 燕飞; Feng 冯, Er-Yuan 二媛; Hou 侯, Fei 飞; Liu 刘, Zhi-Wei 志伟
• Is Part Of: Chinese physics B. Volume 32:Number 4(2023)
• Publication Date: 2023-04-01
• Subjects: electrostatic discharge -- trigger voltage -- latch up -- dV/dt effect; 85.30.De; Physics -- Periodicals; Physics; Periodicals; 530.05
• DOI: 10.1088/1674-1056/ac9607
• Languages: English
• ISSNs: 1674-1056

Abstract

Abstract : Gate-grounded n-channel metal–oxide–semiconductor (GGNMOS) devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction, easy triggering, and low power dissipation. We present a novel I – V characterization of the GGNMOS used as the power clamp in complementary metal–oxide–semiconductor circuits as a result of switching the ESD paths under different impact energies. This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground, and thus should be urgently analyzed and resolved. Transmission-line-pulse, human-body-modal, and light-emission tests were performed to explore the root cause.