Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture. Issue 6 (16th September 2021)

• Record Type: Journal Article
• Authors: Huang, Xiaoying; Guo, Zhichuan; Song, Mangu; Zeng, Xuewen
• Is Part Of: IET computers & digital techniques. Volume 15:Issue 6(2021)
• Page Start: 427
• Page End: 436
• Publication Date: 2021-09-16
• Subjects: field programmable gate arrays -- cryptography -- software architecture -- parallel architectures -- microprocessor chips; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/cdt2.12034
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract: SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This study proposes a CPU‐FPGA co‐designed architecture which offloads the SM3 function on field‐programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115‐flva1517‐2‐e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU‐FPGA‐coupled environment.