Improved ISPP scheme for narrow threshold voltage distribution in 3-D NAND flash memory. (April 2023)

• Record Type: Journal Article
• Authors: Yang, Giho; Park, Chanyang; Nam, Kihoon; Kim, Donghyun; Park, Min Sang; Baek, Rock-Hyun
• Is Part Of: Solid-state electronics. Volume 202(2023)
• Publication Date: 2023-04
• Subjects: Abnormal program cell -- Incremental step pulse programming -- Nonvolatile memory -- 3-D NAND flash -- Threshold voltage distribution; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2023.108607
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Incremental step-pulse programming method is improved to narrow threshold voltage (Vth ) distribution. The improved ISPP (proposed scheme) reduces the Vth distribution width by decreasing the number of abnormal program cells (cells with excessively high Vth ). Proposed scheme has a simple circuit because it controls only the word line voltage. Total number of program pulses is reduced compared to conventional ISPP for the same Vth distribution width. Abstract: Three-dimensional NAND flash technology exhibits a trend of increasing bit density. The narrow threshold voltage (Vth ) distribution of each program state in a chip is important for increasing the number of bits in a multilevel cell (MLC) technique. An abnormal program cell (APC), which is an excessively programmed cell whose Vth overlaps with the next program state, increases the Vth distribution width (Wv ). The wide Vth distribution makes it difficult to distinguish the data stored in each cell and causes data errors. In this study, an improved incremental step pulse programming (ISPP) method to narrow the Vth distribution has been proposed. As the programming step voltage (Vstep ) decreases immediately before the target cells pass the n th program verify level (PVn ), the difference between Vth and PVn decreases, causing a reduction in the number of APCs. Therefore, in the improved ISPP, the Vstep is selectively reduced at the target ISPP steps at which most cells are predicted to be programmed in the next ISPP step for each program state. As a result, the Wv of the improved scheme decreases compared to the conventional scheme with the minimum increase in the total number of program pulses. Larger bit density is feasible by applying improved ISPP, resulting in high-capacity NAND flash memory.