Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis. (April 2023)

• Record Type: Journal Article
• Authors: de Lima Silva, Wenita; do Nascimento Tolêdo, Rodrigo; Gonçalez Filho, Walter; de Moraes Nogueira, Alexandro; Ghedini Der Agopian, Paula; Antonio Martino, Joao
• Is Part Of: Solid-state electronics. Volume 202(2023)
• Publication Date: 2023-04
• Subjects: Tunnel FET (TFET) -- Nanowire -- Line-TFET -- Low-Dropout Voltage Regulator (LDO) -- Process variability -- Analog circuit design; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2023.108611
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Tunnel field-effect transistors with SiGe source composition. Circuit-level comparison between Line and Nanowire TFET for analog applications. gm /ID design using experimental data. Low-dropout voltage regulator design with Tunnel FET. Abstract: This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V −1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V −1 . The comparison between TFET LDOs for gm/ID = 7 V −1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.