Simulation study on single-event burnout reliability of 4H-SiC trench gate MOSFET with combined P-buried layer. (March 2023)

• Record Type: Journal Article
• Authors: Shen, Pei; Wang, Ying; Li, Xing-Ji; Yang, Jian-qun; Zheng, Liang
• Is Part Of: Microelectronics and reliability. Volume 142(2023)
• Publication Date: 2023-03
• Subjects: SiC gate trench MOSFET -- Breakdown voltage (BV) -- Specific on-resistance (Ron, sp) -- Gate drain charge (Qgd, sp) -- Single-event burnout (SEB); Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2023.114931
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this article, the purpose of this numerical study is to investigate the rated 3.3-kV SiC power gate trench MOSFET structure with ground and float p-buried layer (DGF-MOS). The simulation results show the introduction of ground and float p-buried layer and upper drift layer optimized breakdown voltage (BV) the specific on-resistance ( R on, sp ), and gate drain charge ( Q gd, sp ), thus the figure of merit (BV 2 / R on, sp ) is improved by 130 % and the figure of merit ( R on, sp × Q gd, sp ) is reduced 173 % compared with the conventional SiC power gate trench MOSFET (CT-MOS). Additionally, the single-event burnout (SEB) simulation results show that the critical degradation threshold of CT-MOS structure is 900 V at LET = 0.5 pC/μm. The robustness of the DGF-MOS structure design to heavy ions was simulated. The results show that the maximum temperature peaks around the gate trench and substrate junction of the DGF-MOS structure could both be effectively suppressed due to the decrease in electric field peak. Consequently, the DGF-MOS structure showed a severe denaturation threshold of 1500 V, which was 66.6 % higher than that of the CT-MOS structure. Highlights: A method of single-event burnout(SEB) hardening at high linear energy transfer (LET) value range is proposed with combined p-buried layer. The SEB hardening structure shows great Baliga figure of merit (BFOM) and superior high-frequency figure of merit (HF-FOM). The threshold voltage of the proposed structure is increased by 66.6 % compared with the conventional p + -SiC shielding layer power gate trench MOSFET.