Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration. (8th September 2020)

• Record Type: Journal Article
• Authors: Loo, Roger; Jourdain, Anne; Rengo, Gianluca; Porret, Clement; Hikavyy, Andriy Yakovitch; Liebens, Maarten; Becker, Lucas; Storck, Peter; Beyer, Gerald; Beyne, Eric
• Is Part Of: ECS transactions. Volume 98:Number 4(2020)
• Page Start: 157
• Page End: 166
• Publication Date: 2020-09-08
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/09804.0157ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We describe challenges of the epitaxial Si-cap / Si0.75 Ge0.25 // Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75 Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75 Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-capping, even for thinner Si0.75 Ge0.25 layers. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap / Si0.75 Ge0.25 // Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer to wafer bonding and Si-substrate and Si0.75 Ge0.25 backside removal.